The invention relates, in general, to flash memory devices and, more particularly, to a method of manufacturing a flash memory device that reduces an undesirable interference phenomenon.
Semiconductor memory devices for storing data can be largely classified into volatile memory devices or nonvolatile memory devices. Volatile memory devices lose their data when the supply of power thereto is stopped, whereas nonvolatile memory devices retain their data in the absence of power.
Each nonvolatile memory device includes a flash memory device. A unit cell of the flash memory device generally includes an active region defined on a specific region of a semiconductor substrate, a tunnel insulating layer formed on the active region, a floating gate formed on the tunnel insulating layer, a gate interlayer insulating layer formed on the floating gate, and a control gate electrode formed on the gate interlayer insulating layer. In particular, the flash memory device has been widely used for MP3 players, digital cameras, memory for computer BIOS storage, mobile phones, portable data storage devices and so on.
The flash memory cell can store data as voltage externally applied to the control gate electrode is coupled to the floating gate. Accordingly, when storing data for a short period of time and at a low program voltage, the ratio of voltage applied to the control gate electrode to voltage applied to the floating gate must be high. The ratio of voltage applied to the control gate electrode to voltage applied to the floating gate is called the coupling ratio (“CR”). Furthermore, the coupling ratio can be expressed by the ratio of the capacitance of the gate interlayer insulating layer to the sum of the capacitance of the tunnel insulating layer and the gate interlayer insulating layer.
In current flash memory manufacturing methods, the space where a unit active region and a unit field region will be formed narrows as devices become more highly integrated. When a dielectric layer, a control gate and a floating gate are formed within a narrow active space, the distance between the gates is narrowed, so that the interference phenomenon becomes increasingly problematic. In particular, in order to develop a Multi-Level Cell (MLC) in a general NAND flash memory device employing an Advanced Self-Aligned Shallow Trench Isolation (ASA-STI) method, interference charges between the floating gates must be reduced.
A conventional method of manufacturing a flash memory device is briefly described below.
In order to minimize the damage to a semiconductor substrate resulting from an ion implant process, a buffer insulating layer is formed on the semiconductor substrate. The buffer insulating layer is formed from an oxide layer. After the ion implant process is performed, the buffer insulating layer is removed. After a tunnel insulating layer is formed over the semiconductor substrate, an annealing process is performed. The tunnel insulating layer is formed by performing a wet or dry oxidization process at a temperature ranging from 750° C. to 850° C. using H2 or O2. The annealing process is performed in order to eliminate the trap phenomenon occurring at the interface between the semiconductor substrate and the tunnel insulating layer and to increase the data storage ability of the transistor. The annealing process includes a post-anneal process at a temperature ranging from 750° C. to 1100° C. using N2, N2O, or NO.
A first conductive layer for a floating gate is formed on the tunnel insulating layer. The first conductive layer is formed by in-situ implanting a P or B dopant into a source gas of SiH4, Si2H6, or SiH2Cl2. A first hard mask layer having a stack structure of an oxide layer and a nitride layer is formed on the first conductive layer. The first hard mask layer, the first conductive layer, the tunnel insulating layer, and the semiconductor substrate are partially etched by a photo and development processes, thereby forming trenches and also a floating gate consisting of the first conductive layer.
A first insulating layer is formed over the semiconductor substrate including the trenches so that the trenches are filled. The first insulating layer is polished to form isolation layers. The first insulating layer is polished using a High Density Plasma (HDP) oxide layer or Spin on Glass (SOG). In order to control the Effective Field Height (EFH) of the isolation layers, a wet etch process (i.e., a cleaning process) is performed to partially remove the top surface of the isolation layers.
A dielectric layer is formed over the semiconductor substrate including the isolation layers and the first conductive layer. An annealing process and an oxidization process are carried out at a temperature ranging from 600° C. to 900° C. using O2 or H2. A second conductive layer for a control gate and a second hard mask layer are formed over the dielectric layer. The second conductive layer has a stacked structure including a polysilicon layer and a tungsten silicide (WSix) layer or tungsten (W). The second hard mask layer is formed from an oxide layer or a silicon oxynitride (SiON) layer. The second hard mask layer, the second conductive layer, the dielectric layer and the first conductive layer are etched through photo and development processes, thereby forming gates.
Spacers for separating the gates are formed on the sides of the gates. In order to protect a cell gate, a second insulating layer is formed over the semiconductor substrate including the spacers and the gates. The second insulating layer is formed from an oxide layer or a nitride layer.
A first insulating layer having a source contact plug formed therein is formed on the second insulating layer. A second insulating layer having a drain contact plug formed therein is formed over the semiconductor substrate including the source contact plug and the first insulating layer. The source contact plug and the drain contact plug are formed from polysilicon or tungsten. In order to store data in the cell gate and transfer external voltage to the source contact plug and the drain contact plug formed so as to read stored data, metal lines are formed on the second insulating layer.
Today, in a flash memory device, in order to select a specific cell gate, voltage is applied to the SSL and the metal line, and current flows through the cell gate due to a difference between applied voltages. In order for the current to flow through only the cell gate, the select transistor, such as the Source Select Line (SSL) or the drain select line (DSL), are used. However, an interference phenomenon occurs between the select transistor and the cell gate that is the nearest to the select transistor due to voltage applied to turn on/off the select transistor. Accordingly, the current properties of the gate around the select transistor are changed, causing a large amount or small amount of current to flow. This results in defective cell properties.